Tela Innovations, Inc.

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Patent Activity in the Last 10 Years

Technologies

Intl Class Technology Matters Rank in Class
 
  
 
H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR 158210
 
  
 
G06F ELECTRIC DIGITAL DATA PROCESSING 81366
 
  
 
G03F PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR 4100
 
  
 
G11C STATIC STORES 4147
 
  
 
H03K PULSE TECHNIQUE 2129
 
  
 
A43B CHARACTERISTIC FEATURES OF FOOTWEAR; PARTS OF FOOTWEAR134
 
  
 
C23F NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACES 135
 
  
 
G01R MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES 1158

Top Patents (by citation)

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Recent Publications

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Recent Patents

Patent # Title Filing Date Issue Date Intl Class
9917056 Coarse grid design methods and structuresMay 09, 16Mar 13, 18[H01L, G06F, G03F]
9910950 Methods for cell phasing and placement in dynamic array architecture and implementation of the sameAug 22, 16Mar 06, 18[H01L, G06F]
9905576 Semiconductor chip including region having rectangular-shaped gate structures and first metal structuresSep 06, 17Feb 27, 18[H01L, G06F]
9871056 Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the sameDec 23, 16Jan 16, 18[H01L, G06F, G11C]
9859277 Methods, structures, and designs for self-aligning local interconnects used in integrated circuitsJan 13, 16Jan 02, 18[H01L, G06F, G03F]
9818747 Super-self-aligned contacts and method for making the sameMar 08, 16Nov 14, 17[H01L]
9779200 Methods for multi-wire routing and apparatus implementing sameJun 13, 16Oct 03, 17[H01L, G06F]
9754878 Semiconductor chip including a chip level based on a layout that includes both regular and irregular wiresMay 20, 13Sep 05, 17[H01L, G06F]
9741719 Methods, structures, and designs for self-aligning local interconnects used in integrated circuitsJan 14, 16Aug 22, 17[H01L, G06F, G03F]
9711495 Oversized contacts and vias in layout defined by linearly constrained topologyAug 22, 16Jul 18, 17[H01L, G03F]

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Expired/Abandoned/Withdrawn Patents

Patent # Title Status Filing Date Issue/Pub Date Intl Class
8490043 Standard cells having transistors annotated for gate-length biasingExpiredMar 04, 10Jul 16, 13[G06F]
8185865 Methods for gate-length biasing using annotation dataExpiredMar 04, 10May 22, 12[G06F]
8127266 Gate-length biasing for digital circuit optimizationExpiredSep 17, 08Feb 28, 12[G06F]
2011/0156,167 Methods for Consumption of Timing Margin to Reduce Power Utilization in Integrated Circuitry and Device Implementing the SameAbandonedDec 29, 10Jun 30, 11[H01L, G06F]
2010/0107,133 Method for increasing cell uniformity in an integrated circuit by adjusting cell inputs to design processAbandonedOct 23, 08Apr 29, 10[G06F]
7441211 Gate-length biasing for digital circuit optimizationExpiredJun 03, 05Oct 21, 08[G06F]
2007/0033,558 Method and system for reshaping metal wires in VLSI designAbandonedAug 08, 05Feb 08, 07[G06F]
2005/0229,130 Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancementsAbandonedApr 07, 04Oct 13, 05[G06F]

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